Intel Executive publishes the Thunderbolt 5 photo and then deletes it: 80 Gbps and PAM-3

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An executive who visits various research divisions around the world isn’t necessarily new, but with a focus on social media that drives nominated people in each company to keep their followers sitting on the edge of their seats means we get a lot more insight into. how these companies operate. The downside to social media posting is when some images displaying undisclosed information are not checked by public relations or the legal department and we take a look at the next generation of technology. This is what happened today.

Day 1 with the @intel Israel team in the books. Great views … amazing opportunity to see @GetThunderbolt innovation … a tour of the validation lab and time with the team … can’t wait to see what tomorrow brings! pic.twitter.com/GKOddA6TNi

– Gregory M Bryant (@gregorymbryant) August 1, 2021

EVP and GM of Intel’s Client Computing Group, Gregory Bryant, is spending some time at Intel’s research and development facilities in Israel this week on his first Intel overseas trip in 2021. A first post on Sunday morning, showing Bryant’s trip to the gym to overcome jetlag, was followed by another later in the day with Bryant being shown the offices and research. The post contained four photos, but was quickly deleted and replaced by a photo with three (in the tweet above). The removed photo shows some new information on next-generation Thunderbolt technology.

In this image we can see a poster on the wall showing “80G PHY Technology” which means Intel is working on a physical layer (PHY) for 80 Gbps connections. At first this is twice the bandwidth of Thunderbolt 4, which runs at 40 Gbps.

The second line confirms that this is “USB 80G aims to support existing USB-C ecosystem”, which follows that Intel aims to keep the USB-C connector but double the effective bandwidth.

The third line is actually where it gets technically interesting. “The PHY will be based on the new PAM-3 modulation technology.” It’s about how 0s and 1s are transmitted – traditionally called NRZ encoding, which only allows the transmission of a 0 or a 1, or a single bit. Natural progression is a pattern that allows two bits to be transferred, and this is called PAM-4 (Pulse Amplitude Modulation), with the 4 being the demarcation for how many different variants two bits can be seen (or as 00, 01, 10 , or 11). PAM-4, at the same frequency, therefore has twice the bandwidth of an NRZ connection.

So what the hell in PAM-3?

From Teledyne LaCroy on YouTube

PAM-3 is a technology in which the data line can carry a -1, a 0 or a +1. What the system does is actually combine two PAM-3 transmissions into one 3-bit data signal, for example 000 is a -1 followed by a -1. This gets complex, so here’s a table:

AnandTech PAM-3 encoding Transmission 1 Transmission 2 000 -1 -1 001 -1 0 010 -1 1 011 0 -1 100 0 1 101 1 -1 110 1 0 111 1 1 Not used 0 0

When we compare NRZ with PAM-3 and PAM-4, we can see that the data transfer rate for PAM-3 is in the middle of NRZ and PAM-4. The reason why PAM-3 is used in this case is to get that increased bandwidth without the additional limitations that PAM-4 requires to be enabled.

NRZ vs PAM-3 vs PAM4 AnandTech Bit Cycles Bits per cycle NRZ 1 1 1 PAM-3 3 2 1.5 PAM-4 2 1 2

PAM-3 has similar limitations to NRZ.

The last line on this image is'[something] The N6 test chip focused on the new PHY technology is working in [the lab and] showing promising results’. The first word I thought was TSMC, but it must have roughly the same width as “The” on the line above. So it doesn’t look like I’m right there, but N6 is a TSMC node.

Intel’s goal with Thunderbolt will be both to drive bandwidth, power and utility, but even right now it appears that keeping it at the USB-C standard will be a vital part of keeping the technology useful for users who can rely on USB connections. -C standard. Right now Intel’s TB4 is a superset that includes USB4, so we might see another situation where TB5 is ready to be a USB5 superset as well, however it appears that USB standards are slower to implement than TB standards in this moment.

Special thanks to David Schor of WikiChip for reporting.

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